Current view: top level - main - pm_sampleMean@routines.F90 (source / functions) Hit Total Coverage Test: ParaMonte 2.0.0 :: Serial Fortran - Code Coverage Report Lines: 528 528 100.0 % Date: 2024-04-08 03:18:57 Functions: 264 264 100.0 % Legend: Lines: hit not hit

Function Name	Hit count
__pm_samplemean_MOD_getmeanall_wno_d1_ck1	4691
__pm_samplemean_MOD_getmeanall_wno_d1_ck2	4600
__pm_samplemean_MOD_getmeanall_wno_d1_ck3	4600
__pm_samplemean_MOD_getmeanall_wno_d1_ck4	4600
__pm_samplemean_MOD_getmeanall_wno_d1_rk1	4855
__pm_samplemean_MOD_getmeanall_wno_d1_rk2	4683
__pm_samplemean_MOD_getmeanall_wno_d1_rk3	4637
__pm_samplemean_MOD_getmeanall_wno_d1_rk4	4637
__pm_samplemean_MOD_getmeanall_wno_d2_ck1	356
__pm_samplemean_MOD_getmeanall_wno_d2_ck2	350
__pm_samplemean_MOD_getmeanall_wno_d2_ck3	350
__pm_samplemean_MOD_getmeanall_wno_d2_ck4	350
__pm_samplemean_MOD_getmeanall_wno_d2_rk1	357
__pm_samplemean_MOD_getmeanall_wno_d2_rk2	350
__pm_samplemean_MOD_getmeanall_wno_d2_rk3	350
__pm_samplemean_MOD_getmeanall_wno_d2_rk4	350
__pm_samplemean_MOD_getmeanall_wti_d1_ck1	405
__pm_samplemean_MOD_getmeanall_wti_d1_ck2	350
__pm_samplemean_MOD_getmeanall_wti_d1_ck3	350
__pm_samplemean_MOD_getmeanall_wti_d1_ck4	350
__pm_samplemean_MOD_getmeanall_wti_d1_rk1	516
__pm_samplemean_MOD_getmeanall_wti_d1_rk2	350
__pm_samplemean_MOD_getmeanall_wti_d1_rk3	350
__pm_samplemean_MOD_getmeanall_wti_d1_rk4	350
__pm_samplemean_MOD_getmeanall_wti_d2_ck1	350
__pm_samplemean_MOD_getmeanall_wti_d2_ck2	350
__pm_samplemean_MOD_getmeanall_wti_d2_ck3	350
__pm_samplemean_MOD_getmeanall_wti_d2_ck4	350
__pm_samplemean_MOD_getmeanall_wti_d2_rk1	352
__pm_samplemean_MOD_getmeanall_wti_d2_rk2	350
__pm_samplemean_MOD_getmeanall_wti_d2_rk3	350
__pm_samplemean_MOD_getmeanall_wti_d2_rk4	350
__pm_samplemean_MOD_getmeanall_wtr_d1_ck1	457
__pm_samplemean_MOD_getmeanall_wtr_d1_ck2	400
__pm_samplemean_MOD_getmeanall_wtr_d1_ck3	400
__pm_samplemean_MOD_getmeanall_wtr_d1_ck4	400
__pm_samplemean_MOD_getmeanall_wtr_d1_rk1	571
__pm_samplemean_MOD_getmeanall_wtr_d1_rk2	400
__pm_samplemean_MOD_getmeanall_wtr_d1_rk3	400
__pm_samplemean_MOD_getmeanall_wtr_d1_rk4	400
__pm_samplemean_MOD_getmeanall_wtr_d2_ck1	350
__pm_samplemean_MOD_getmeanall_wtr_d2_ck2	350
__pm_samplemean_MOD_getmeanall_wtr_d2_ck3	350
__pm_samplemean_MOD_getmeanall_wtr_d2_ck4	350
__pm_samplemean_MOD_getmeanall_wtr_d2_rk1	356
__pm_samplemean_MOD_getmeanall_wtr_d2_rk2	350
__pm_samplemean_MOD_getmeanall_wtr_d2_rk3	350
__pm_samplemean_MOD_getmeanall_wtr_d2_rk4	350
__pm_samplemean_MOD_getmeandim_wno_d1_ck1	305
__pm_samplemean_MOD_getmeandim_wno_d1_ck2	300
__pm_samplemean_MOD_getmeandim_wno_d1_ck3	300
__pm_samplemean_MOD_getmeandim_wno_d1_ck4	300
__pm_samplemean_MOD_getmeandim_wno_d1_rk1	306
__pm_samplemean_MOD_getmeandim_wno_d1_rk2	300
__pm_samplemean_MOD_getmeandim_wno_d1_rk3	300
__pm_samplemean_MOD_getmeandim_wno_d1_rk4	300
__pm_samplemean_MOD_getmeandim_wno_d2_ck1	3559
__pm_samplemean_MOD_getmeandim_wno_d2_ck2	3450
__pm_samplemean_MOD_getmeandim_wno_d2_ck3	3450
__pm_samplemean_MOD_getmeandim_wno_d2_ck4	3450
__pm_samplemean_MOD_getmeandim_wno_d2_rk1	3742
__pm_samplemean_MOD_getmeandim_wno_d2_rk2	3450
__pm_samplemean_MOD_getmeandim_wno_d2_rk3	3450
__pm_samplemean_MOD_getmeandim_wno_d2_rk4	3450
__pm_samplemean_MOD_getmeandim_wti_d1_ck1	350
__pm_samplemean_MOD_getmeandim_wti_d1_ck2	350
__pm_samplemean_MOD_getmeandim_wti_d1_ck3	350
__pm_samplemean_MOD_getmeandim_wti_d1_ck4	350
__pm_samplemean_MOD_getmeandim_wti_d1_rk1	351
__pm_samplemean_MOD_getmeandim_wti_d1_rk2	350
__pm_samplemean_MOD_getmeandim_wti_d1_rk3	350
__pm_samplemean_MOD_getmeandim_wti_d1_rk4	350
__pm_samplemean_MOD_getmeandim_wti_d2_ck1	955
__pm_samplemean_MOD_getmeandim_wti_d2_ck2	900
__pm_samplemean_MOD_getmeandim_wti_d2_ck3	900
__pm_samplemean_MOD_getmeandim_wti_d2_ck4	900
__pm_samplemean_MOD_getmeandim_wti_d2_rk1	1139
__pm_samplemean_MOD_getmeandim_wti_d2_rk2	900
__pm_samplemean_MOD_getmeandim_wti_d2_rk3	900
__pm_samplemean_MOD_getmeandim_wti_d2_rk4	900
__pm_samplemean_MOD_getmeandim_wtr_d1_ck1	302
__pm_samplemean_MOD_getmeandim_wtr_d1_ck2	300
__pm_samplemean_MOD_getmeandim_wtr_d1_ck3	300
__pm_samplemean_MOD_getmeandim_wtr_d1_ck4	300
__pm_samplemean_MOD_getmeandim_wtr_d1_rk1	306
__pm_samplemean_MOD_getmeandim_wtr_d1_rk2	300
__pm_samplemean_MOD_getmeandim_wtr_d1_rk3	300
__pm_samplemean_MOD_getmeandim_wtr_d1_rk4	300
__pm_samplemean_MOD_getmeandim_wtr_d2_ck1	955
__pm_samplemean_MOD_getmeandim_wtr_d2_ck2	900
__pm_samplemean_MOD_getmeandim_wtr_d2_ck3	900
__pm_samplemean_MOD_getmeandim_wtr_d2_ck4	900
__pm_samplemean_MOD_getmeandim_wtr_d2_rk1	1143
__pm_samplemean_MOD_getmeandim_wtr_d2_rk2	900
__pm_samplemean_MOD_getmeandim_wtr_d2_rk3	900
__pm_samplemean_MOD_getmeandim_wtr_d2_rk4	900
__pm_samplemean_MOD_getmeanmergednew_d0_ck1	50
__pm_samplemean_MOD_getmeanmergednew_d0_ck2	50
__pm_samplemean_MOD_getmeanmergednew_d0_ck3	50
__pm_samplemean_MOD_getmeanmergednew_d0_ck4	50
__pm_samplemean_MOD_getmeanmergednew_d0_rk1	80
__pm_samplemean_MOD_getmeanmergednew_d0_rk2	50
__pm_samplemean_MOD_getmeanmergednew_d0_rk3	50
__pm_samplemean_MOD_getmeanmergednew_d0_rk4	50
__pm_samplemean_MOD_getmeanmergednew_d1_ck1	50
__pm_samplemean_MOD_getmeanmergednew_d1_ck2	50
__pm_samplemean_MOD_getmeanmergednew_d1_ck3	50
__pm_samplemean_MOD_getmeanmergednew_d1_ck4	50
__pm_samplemean_MOD_getmeanmergednew_d1_rk1	80
__pm_samplemean_MOD_getmeanmergednew_d1_rk2	50
__pm_samplemean_MOD_getmeanmergednew_d1_rk3	50
__pm_samplemean_MOD_getmeanmergednew_d1_rk4	50
__pm_samplemean_MOD_setmeanall_wno_d1_ck1	4791
__pm_samplemean_MOD_setmeanall_wno_d1_ck2	4700
__pm_samplemean_MOD_setmeanall_wno_d1_ck3	4700
__pm_samplemean_MOD_setmeanall_wno_d1_ck4	4700
__pm_samplemean_MOD_setmeanall_wno_d1_rk1	4959
__pm_samplemean_MOD_setmeanall_wno_d1_rk2	4783
__pm_samplemean_MOD_setmeanall_wno_d1_rk3	4737
__pm_samplemean_MOD_setmeanall_wno_d1_rk4	4737
__pm_samplemean_MOD_setmeanall_wno_d2_ck1	456
__pm_samplemean_MOD_setmeanall_wno_d2_ck2	450
__pm_samplemean_MOD_setmeanall_wno_d2_ck3	450
__pm_samplemean_MOD_setmeanall_wno_d2_ck4	450
__pm_samplemean_MOD_setmeanall_wno_d2_rk1	458
__pm_samplemean_MOD_setmeanall_wno_d2_rk2	450
__pm_samplemean_MOD_setmeanall_wno_d2_rk3	450
__pm_samplemean_MOD_setmeanall_wno_d2_rk4	450
__pm_samplemean_MOD_setmeanall_wno_xy_ck1	100
__pm_samplemean_MOD_setmeanall_wno_xy_ck2	100
__pm_samplemean_MOD_setmeanall_wno_xy_ck3	100
__pm_samplemean_MOD_setmeanall_wno_xy_ck4	100
__pm_samplemean_MOD_setmeanall_wno_xy_rk1	102
__pm_samplemean_MOD_setmeanall_wno_xy_rk2	2505
__pm_samplemean_MOD_setmeanall_wno_xy_rk3	100
__pm_samplemean_MOD_setmeanall_wno_xy_rk4	100
__pm_samplemean_MOD_setmeanall_wti_d1_ck1	505
__pm_samplemean_MOD_setmeanall_wti_d1_ck2	450
__pm_samplemean_MOD_setmeanall_wti_d1_ck3	450
__pm_samplemean_MOD_setmeanall_wti_d1_ck4	450
__pm_samplemean_MOD_setmeanall_wti_d1_rk1	616
__pm_samplemean_MOD_setmeanall_wti_d1_rk2	450
__pm_samplemean_MOD_setmeanall_wti_d1_rk3	450
__pm_samplemean_MOD_setmeanall_wti_d1_rk4	450
__pm_samplemean_MOD_setmeanall_wti_d2_ck1	450
__pm_samplemean_MOD_setmeanall_wti_d2_ck2	450
__pm_samplemean_MOD_setmeanall_wti_d2_ck3	450
__pm_samplemean_MOD_setmeanall_wti_d2_ck4	450
__pm_samplemean_MOD_setmeanall_wti_d2_rk1	452
__pm_samplemean_MOD_setmeanall_wti_d2_rk2	450
__pm_samplemean_MOD_setmeanall_wti_d2_rk3	450
__pm_samplemean_MOD_setmeanall_wti_d2_rk4	450
__pm_samplemean_MOD_setmeanall_wti_xy_ck1	100
__pm_samplemean_MOD_setmeanall_wti_xy_ck2	100
__pm_samplemean_MOD_setmeanall_wti_xy_ck3	100
__pm_samplemean_MOD_setmeanall_wti_xy_ck4	100
__pm_samplemean_MOD_setmeanall_wti_xy_rk1	101
__pm_samplemean_MOD_setmeanall_wti_xy_rk2	1302
__pm_samplemean_MOD_setmeanall_wti_xy_rk3	100
__pm_samplemean_MOD_setmeanall_wti_xy_rk4	100
__pm_samplemean_MOD_setmeanall_wtr_d1_ck1	558
__pm_samplemean_MOD_setmeanall_wtr_d1_ck2	500
__pm_samplemean_MOD_setmeanall_wtr_d1_ck3	500
__pm_samplemean_MOD_setmeanall_wtr_d1_ck4	500
__pm_samplemean_MOD_setmeanall_wtr_d1_rk1	673
__pm_samplemean_MOD_setmeanall_wtr_d1_rk2	500
__pm_samplemean_MOD_setmeanall_wtr_d1_rk3	500
__pm_samplemean_MOD_setmeanall_wtr_d1_rk4	500
__pm_samplemean_MOD_setmeanall_wtr_d2_ck1	450
__pm_samplemean_MOD_setmeanall_wtr_d2_ck2	450
__pm_samplemean_MOD_setmeanall_wtr_d2_ck3	450
__pm_samplemean_MOD_setmeanall_wtr_d2_ck4	450
__pm_samplemean_MOD_setmeanall_wtr_d2_rk1	457
__pm_samplemean_MOD_setmeanall_wtr_d2_rk2	450
__pm_samplemean_MOD_setmeanall_wtr_d2_rk3	450
__pm_samplemean_MOD_setmeanall_wtr_d2_rk4	450
__pm_samplemean_MOD_setmeanall_wtr_xy_ck1	100
__pm_samplemean_MOD_setmeanall_wtr_xy_ck2	100
__pm_samplemean_MOD_setmeanall_wtr_xy_ck3	100
__pm_samplemean_MOD_setmeanall_wtr_xy_ck4	100
__pm_samplemean_MOD_setmeanall_wtr_xy_rk1	103
__pm_samplemean_MOD_setmeanall_wtr_xy_rk2	3702
__pm_samplemean_MOD_setmeanall_wtr_xy_rk3	100
__pm_samplemean_MOD_setmeanall_wtr_xy_rk4	100
__pm_samplemean_MOD_setmeandim_wno_d1_ck1	405
__pm_samplemean_MOD_setmeandim_wno_d1_ck2	400
__pm_samplemean_MOD_setmeandim_wno_d1_ck3	400
__pm_samplemean_MOD_setmeandim_wno_d1_ck4	400
__pm_samplemean_MOD_setmeandim_wno_d1_rk1	408
__pm_samplemean_MOD_setmeandim_wno_d1_rk2	400
__pm_samplemean_MOD_setmeandim_wno_d1_rk3	400
__pm_samplemean_MOD_setmeandim_wno_d1_rk4	400
__pm_samplemean_MOD_setmeandim_wno_d2_ck1	3709
__pm_samplemean_MOD_setmeandim_wno_d2_ck2	3600
__pm_samplemean_MOD_setmeandim_wno_d2_ck3	3600
__pm_samplemean_MOD_setmeandim_wno_d2_ck4	3600
__pm_samplemean_MOD_setmeandim_wno_d2_rk1	3897
__pm_samplemean_MOD_setmeandim_wno_d2_rk2	6911
__pm_samplemean_MOD_setmeandim_wno_d2_rk3	3600
__pm_samplemean_MOD_setmeandim_wno_d2_rk4	3600
__pm_samplemean_MOD_setmeandim_wti_d1_ck1	450
__pm_samplemean_MOD_setmeandim_wti_d1_ck2	450
__pm_samplemean_MOD_setmeandim_wti_d1_ck3	450
__pm_samplemean_MOD_setmeandim_wti_d1_ck4	450
__pm_samplemean_MOD_setmeandim_wti_d1_rk1	451
__pm_samplemean_MOD_setmeandim_wti_d1_rk2	450
__pm_samplemean_MOD_setmeandim_wti_d1_rk3	450
__pm_samplemean_MOD_setmeandim_wti_d1_rk4	450
__pm_samplemean_MOD_setmeandim_wti_d2_ck1	1106
__pm_samplemean_MOD_setmeandim_wti_d2_ck2	1050
__pm_samplemean_MOD_setmeandim_wti_d2_ck3	1050
__pm_samplemean_MOD_setmeandim_wti_d2_ck4	1050
__pm_samplemean_MOD_setmeandim_wti_d2_rk1	1994
__pm_samplemean_MOD_setmeandim_wti_d2_rk2	52858
__pm_samplemean_MOD_setmeandim_wti_d2_rk3	1050
__pm_samplemean_MOD_setmeandim_wti_d2_rk4	1050
__pm_samplemean_MOD_setmeandim_wtr_d1_ck1	402
__pm_samplemean_MOD_setmeandim_wtr_d1_ck2	400
__pm_samplemean_MOD_setmeandim_wtr_d1_ck3	400
__pm_samplemean_MOD_setmeandim_wtr_d1_ck4	400
__pm_samplemean_MOD_setmeandim_wtr_d1_rk1	407
__pm_samplemean_MOD_setmeandim_wtr_d1_rk2	400
__pm_samplemean_MOD_setmeandim_wtr_d1_rk3	400
__pm_samplemean_MOD_setmeandim_wtr_d1_rk4	400
__pm_samplemean_MOD_setmeandim_wtr_d2_ck1	1106
__pm_samplemean_MOD_setmeandim_wtr_d2_ck2	1050
__pm_samplemean_MOD_setmeandim_wtr_d2_ck3	1050
__pm_samplemean_MOD_setmeandim_wtr_d2_ck4	1050
__pm_samplemean_MOD_setmeandim_wtr_d2_rk1	1303
__pm_samplemean_MOD_setmeandim_wtr_d2_rk2	6006
__pm_samplemean_MOD_setmeandim_wtr_d2_rk3	1050
__pm_samplemean_MOD_setmeandim_wtr_d2_rk4	1050
__pm_samplemean_MOD_setmeanmergednew_d0_ck1	100
__pm_samplemean_MOD_setmeanmergednew_d0_ck2	100
__pm_samplemean_MOD_setmeanmergednew_d0_ck3	100
__pm_samplemean_MOD_setmeanmergednew_d0_ck4	100
__pm_samplemean_MOD_setmeanmergednew_d0_rk1	160
__pm_samplemean_MOD_setmeanmergednew_d0_rk2	100
__pm_samplemean_MOD_setmeanmergednew_d0_rk3	100
__pm_samplemean_MOD_setmeanmergednew_d0_rk4	100
__pm_samplemean_MOD_setmeanmergednew_d1_ck1	100
__pm_samplemean_MOD_setmeanmergednew_d1_ck2	100
__pm_samplemean_MOD_setmeanmergednew_d1_ck3	100
__pm_samplemean_MOD_setmeanmergednew_d1_ck4	100
__pm_samplemean_MOD_setmeanmergednew_d1_rk1	160
__pm_samplemean_MOD_setmeanmergednew_d1_rk2	100
__pm_samplemean_MOD_setmeanmergednew_d1_rk3	100
__pm_samplemean_MOD_setmeanmergednew_d1_rk4	100
__pm_samplemean_MOD_setmeanmergedold_d0_ck1	50
__pm_samplemean_MOD_setmeanmergedold_d0_ck2	50
__pm_samplemean_MOD_setmeanmergedold_d0_ck3	50
__pm_samplemean_MOD_setmeanmergedold_d0_ck4	50
__pm_samplemean_MOD_setmeanmergedold_d0_rk1	80
__pm_samplemean_MOD_setmeanmergedold_d0_rk2	50
__pm_samplemean_MOD_setmeanmergedold_d0_rk3	50
__pm_samplemean_MOD_setmeanmergedold_d0_rk4	50
__pm_samplemean_MOD_setmeanmergedold_d1_ck1	50
__pm_samplemean_MOD_setmeanmergedold_d1_ck2	50
__pm_samplemean_MOD_setmeanmergedold_d1_ck3	50
__pm_samplemean_MOD_setmeanmergedold_d1_ck4	50
__pm_samplemean_MOD_setmeanmergedold_d1_rk1	80
__pm_samplemean_MOD_setmeanmergedold_d1_rk2	50
__pm_samplemean_MOD_setmeanmergedold_d1_rk3	50
__pm_samplemean_MOD_setmeanmergedold_d1_rk4	50

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